A New Method for Lowering the Error Floors of Non-binary LDPC Codes
نویسندگان
چکیده
In this paper, we propose a new method for improving the performance of non-binary low-density parity-check (LDPC) codes of short block lengths at the high signal-to-noise ratio (SNR) region. In addition to the standard short cycle removal methods, we consider two new optimization criteria unique to non-binary codes. For each individual short cycle, we assign nonbinary values to the associated non-zero elements in the paritycheck matrix in order to optimize the decoding performance. For overlapped short cycles, the non-zero elements are assigned by first improving the minimum distance and then optimizing the decoding performance. The additional optimization requires only moderate increase in the code design complexity. For rate1/2, short-block-length (1008-bit) LDPC codes over GF(16) and GF(32), simulations show that, using the proposed method, the error floor can be considerably lowered without any performance degradation in the waterfall region.
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